| 摘要 |
PROBLEM TO BE SOLVED: To solve a problem in the conventional case wherein important restriction on design of a flash memory device, and especially, restriction regarding reduction of cell dimension and size of process specification are generated by a high voltage which is used for charging and discharging a floating gate. SOLUTION: This flash EPROM integrated circuit structure is provided with a semiconductor substrate of a first conductivity type, a first well of a second conductivity type in the substrate, and a second well of a first conductivity type in the first well. A flash EPROM cell is formed in the second well. In a charging method of the flash EPROM integrated circuit structure, negative potential can be applied to at least one out of a source and a drain during operation for charging a floating gate of a cell, so that the magnitude of a high positive voltage to be applied to the gate in order to generate an F-N tunnel phenomenon in a cell to be charged can be decreased essentially. |
