| 摘要 |
<p>PROBLEM TO BE SOLVED: To restrain an increase in the area of a semiconductor storage device by reducing a well boundary part of a memory cell array. SOLUTION: This semiconductor storage device is provided with a semiconductor substrate 20 of first conductivity, a first well region 2 of second conductivity which is formed on the semiconductor substrate 20, a second well region 7 of first conductivity which is formed in the first well region 2, a third well region 7 of first conductivity which is formed in the first well region 2, a memory cell array 15 wherein memory cells 8 having a MOS structure are arranged in a matrix form in the second well region 7 and the third well region 7, and selection circuits 3, 5, 9, 10, 11, 12, 13, 14 which select the memory cells 8 on the basis of a column address and a row address.</p> |
