| 摘要 |
A binary counter consisting of a binary adder and flip-flops, the Q outputs of the flip-flops being connected to the A inputs of the adder, the SIGMA outputs of the adder being connected to the D inputs of the flip-flops. By connecting the B input of the adder to any of several combination of source voltages, the counter may be used as a down counter or an up counter wherein the sequence of steps up or down is selectively variable.
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