METHOD AND DEVICE FOR OPTIMIZING BUS IN PROCESSOR LOCAL BUS SYSTEM

摘要

PROBLEM TO BE SOLVED: To provide architecture by which a bus usage amount is optimized concerning data reading transfer and data writing transfer and which is provided with an improved device for interfacing with an on-chip bus to be used in an SOC performing state. SOLUTION: A master engine performs the transfer transaction of N-byte data on the bus of a PLB system. The type of reading or writing data transfer to be performed by the master engine is decided to optimize a bus operation in response to a transfer request which is asynchronously received from the device connected to the bus. A request type deciding function is used for it. Data is asynchronously transferred between the device and the bus through the use of a FIFO in accordance with the decided transfer type.