ASYNCHRONOUS DATA TRANSFER CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide an asynchronous data transfer circuit for surely transferring parallel data with excellent precision even in the case of parallel data transfer between asynchronizing circuits. SOLUTION: A load/hold signal generating circuit 6 generates a load/hold signal 5 which is obtained by synchronization with a transmission side clock 3 and widening a width based on a read signal 1 outputted from a reception side through the use of a flip-flop 8. A parallel data transfer circuit 7 inputs the load/hold signal 5 to the respective L/H terminals of flip-flops 9 and 10 which are connected in parallel. When parallel data 2 from a transmission side is transferred by synchronization with the transmission side clock 3, the load/hold signal 5 is given after the rising edge of the transmission side clock 3 so as to eliminate the bit transformation of parallel data 2 from the transmission side. A set-up time for holding data at the reception side is sufficiently guaranteed even when a read signal 1 is inputted to the transmission side by any timing.