发明名称 Semiconductor memory
摘要 First of all, bit lines and sense amplifier nodes are precharged separately. Thereafter, the precharged state of the bit lines is canceled, and the gate level of each charge transfer transistor is raised to an appropriate value while the sense amplifier nodes are maintained in the precharged state, thereby copying the threshold voltage difference between the charge transfer transistors as the potential difference between the pair of bit lines. The precharged state of the sense amplifier nodes is then canceled, and the gate level of the charge transfer transistor is raised to an appropriate value, thereby reading out data from the memory cell to the sense amplifier nodes.
申请公布号 US2002060924(A1) 申请公布日期 2002.05.23
申请号 US20010988738 申请日期 2001.11.20
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 ITO HIROSHI
分类号 G11C11/409;G11C7/06;G11C7/12;G11C11/4091;G11C11/4094;(IPC1-7):G11C11/24 主分类号 G11C11/409
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