摘要 |
The invention relates to an integrated magnetoresistive semiconductor memory system, in which n memory cells that comprise two magnetic layers (WML, HML), each separated by a thin dielectric barrier (TL), and associated word lines (WL) and bit lines (BL) that cross one another are vertically stacked in n layers (L1, L2, L3, L4). The system further comprises a decoding circuit for selecting one of the n memory layers (L1 - L4). Said decoding circuit, on both ends of a word line (WL) or a bit line (BL), is provided with one arrangement each that consists of n layer selecting transistors (N0 - N3, N4 - N7) for selecting one of the n memory layers (L1 - L4), and with a line selection transistor (P0, P1) for selecting the respective horizontal word line or bit line (WL or BL) on which a voltage (V) is to be impressed. |
申请人 |
INFINEON TECHNOLOGIES AG;BOEHM, THOMAS;ROEHR, THOMAS;HOENIGSCHMID, HEINZ |
发明人 |
BOEHM, THOMAS;ROEHR, THOMAS;HOENIGSCHMID, HEINZ |