| 摘要 |
An integrated circuit includes an address register, clocked by the clock signal corresponding to the TAP, used to address a control/status register within the integrated circuit. The address register receives a signal indicating that an address is to be loaded into the address register. A control circuit is coupled to receive the signal and to generate a second signal responsive to the address register being loaded. A shadow register, clocked by the clock signal of the integrated circuit, is coupled to receive the second signal and to load a value from the control/status register addressed by the address loaded into the address register responsive to the second signal. In this manner, a valid value from the addressed register is synchronized in the clock domain of the addressed register. The value for the shadow register may subsequently be synchronized into the clock domain of the TAP, and subsequently transferred out of the integrated circuit via the test interface. |
