发明名称 Synchronous dram utilizable as shared memory
摘要 A memory array is divided into a plurality of blocks. A plurality of mode storage units is so disposed as to correspond to the memory blocks. When a plurality of controllers outputs a mode setting instruction at the time of making of power, a setting unit 113 sets control information designated by the mode setting instruction to the corresponding mode storage unit. When different controllers gain access to a synchronous DRAM, an access operation is executed for the corresponding memory block in accordance with the control information.
申请公布号 US2002062428(A1) 申请公布日期 2002.05.23
申请号 US20010816236 申请日期 2001.03.26
申请人 FUJITSU LIMITED 发明人 ASAKAWA MASASHI;MATSUI NORIYUKI;KOUSAKI YASUO;TAKAMURA SHIGERU
分类号 G11C11/407;G06F12/00;G06F12/06;G06F13/42;G11C11/401;(IPC1-7):G06F12/02 主分类号 G11C11/407
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