发明名称 |
Device and method for digitally generating equidistant synchronous frequency-multiplied clock pulses |
摘要 |
Uniform distribution of a correction determined by a PLL over the subordinate clock signals is undertaken by dividing a phase-regulated value by the number of subordinate clock signals. Division by way of successive addition is performed such that time conflicts with subordinate clock signals generated in real time are successfully avoided despite the required time duration of such a division. The synchronicity can be further raised by also uniformly distributing a division remainder. A particularly effective implementation of this division employs subsequent rounding for real time use.
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申请公布号 |
US2002061083(A1) |
申请公布日期 |
2002.05.23 |
申请号 |
US20010918614 |
申请日期 |
2001.07.31 |
申请人 |
KAESDORF OSWALD;WANNER DIETMAR |
发明人 |
KAESDORF OSWALD;WANNER DIETMAR |
分类号 |
H03L7/085;H03L7/099;H04J3/06;(IPC1-7):H04L7/00;H04L25/40;H04L25/00;H04L7/04 |
主分类号 |
H03L7/085 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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