发明名称 |
Semiconductor trench device with enhanced gate oxide integrity structure |
摘要 |
A method for making trench DMOS is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench disposed in the active region of the device and a second trench disposed in the termination region of the device. In accordance with the method, mask techniques are used to thicken the oxide layer in the vicinity of the top corner of the second trench, thereby compensating for the thinning of this region (and the accompanying reduction in breakdown voltage) that occurs due to the two-dimensional oxidation during the manufacturing process.
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申请公布号 |
US2002061623(A1) |
申请公布日期 |
2002.05.23 |
申请号 |
US20010042558 |
申请日期 |
2001.11.20 |
申请人 |
HSHIEH FWU-IUAN;SO KOON CHONG;TSUI YAN MAN |
发明人 |
HSHIEH FWU-IUAN;SO KOON CHONG;TSUI YAN MAN |
分类号 |
H01L29/06;H01L21/336;H01L29/40;H01L29/423;H01L29/78;(IPC1-7):H01L21/336 |
主分类号 |
H01L29/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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