发明名称 TEST ARCHITECTURE
摘要 PROBLEM TO BE SOLVED: To provide a boundary test architecture usable for executing a boundary test in an integrated circuit when the integrated circuit is in an operation mode. SOLUTION: This test architecture used in the integrated circuit is equipped with an application logic circuit of the integrated circuit for executing a desired function, having an input terminal for carrying input data and an output terminal for carrying output data, a aerial scanning route which is a serial scanning route formed by a resistor of the integrated circuit, including one or more comparison data resisters for holding comparison data loaded continuously from the scanning route, and a comparison logic for generating a comparison signal corresponding to comparison between the comparison data of the comparison data resisters and the data of the application logic circuit, connected to the application logic circuit and the comparison data resisters.
申请公布号 JP2002148311(A) 申请公布日期 2002.05.22
申请号 JP20010268995 申请日期 2001.09.05
申请人 TEXAS INSTR INC <TI> 发明人 WHETSEL LEE D
分类号 G01R31/28;B42D15/00;G01R31/317;G01R31/3185;G06F11/22;H01L21/66;H01L21/822;H01L27/04 主分类号 G01R31/28
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