| 摘要 |
PURPOSE: A semiconductor device is provided to decrease the number of fabricating processes by simultaneously forming a lower electrode of a capacitor in a memory cell region and a metal interconnection in a peripheral circuit while using expensive metal layers like Pt, Ru, Ir, Rh and Os, and to reduce fabricating cost by efficiently using the expensive metal layer. CONSTITUTION: A cell region and a peripheral region are defined in a semiconductor substrate(41) having a transistor including a source/drain. The first interlayer dielectric(42) and an etch stop layer(43) are stacked to form a contact hole of a predetermined width in a predetermined region of the semiconductor substrate. The second interlayer dielectric(44) has a hole of which the width is broader than that of the contact hole. A barrier metal layer(46) is formed in the contact hole and on the surface of the hole. The lower electrode(47a) of the capacitor formed in the cell region and the metal interconnection formed in the peripheral region are surrounded by the barrier metal layer in the contact hole and the hole, wherein the metal interconnection is made of the same material as the lower electrode of the capacitor. A dielectric layer(48) is formed along the upper portion of the lower electrode. An upper electrode(49) of the capacitor is formed on the dielectric layer.
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