发明名称 Phase-locked loop circuit with high lock speed and stability
摘要 A phase-locked loop circuit includes a voltage-controlled oscillator that includes a series circuit having a P-channel transistor, N-channel transistor, a third resistor and a first resistor connected in series in this order; a second resistor connected in parallel with a series circuit of the N-channel transistor and the third resistor; and an operational amplifier having its non-inverting input terminal connected to an output terminal of a lowpass filter, its inverting input terminal connected to a connected point of the third resistor and first resistor, and its output terminal connected to a gate of the N-channel transistor. The variable region of the resistance of the parallel circuit consisting of the N-channel transistor and the third and first resistors can be limited, which in turn enables the variable region of the control voltage of the voltage-controlled oscillator including a locking control voltage to be limited to a desired range. This makes it possible to limit the oscillation frequency of the voltage-controlled oscillator determined by the voltage signal fed from the lowpass filter to a desired range, and to increase its lock speed and stability at the same time.
申请公布号 US6392497(B1) 申请公布日期 2002.05.21
申请号 US20010761849 申请日期 2001.01.18
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA;MITSUBISHI ELECTRIC SYSTEM LSI DESIGN CORPORATION 发明人 TAKIKAWA YUTAKA
分类号 H03L7/089;H03L7/093;H03L7/099;H03L7/107;H03L7/18;(IPC1-7):H03L7/08 主分类号 H03L7/089
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