| 摘要 |
The present invention discloses an NMOS coupling circuit for preventing gate junction breakdown of a flash memory. The present invention adds at least one isolating stage between a conducting stage and a high voltage HV of the prior coupling circuit, and the addition generates a benefit that the voltage difference of the high voltage HV is burdened by both the conducting stage and the isolating stage of the coupling circuit. In other words, the voltage difference in the gate junction of the conducting stage will be reduced, and the probability of punching through a transistor will also be reduced. For reducing the effect of an instant voltage difference when the high voltage HV is enabled, the present invention electrically connects one end of a diode to the gate of the isolating stage, and electrically connects another end of the diode to a lower power source VDD. Therefore, the magnitude of the VDD will be reduced from the instant voltage difference to protect the isolating stage from damaging when the high voltage HV is enabled.
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