发明名称 |
Method for forming overlay verniers for semiconductor devices |
摘要 |
The present invention discloses a method for forming an overlay vernier that can prevents deformation of the mother vernier. The method comprises the steps of: forming a planarization film on a wafer where a predetermined basic substructure has been formed; etching the planarization film to expose a predetermined region of a scribe line of the wafer where the overlay vernier will be formed; depositing a first polysilicon layer on the planarization film and the exposed wafer region; polishing the first polysilicon layer until the surface of the planarization film is exposed; forming an interlayer insulating film on the planarization film and the remained first polysilicon layer; etching the interlayer insulating film to expose a region of the first polysilicon layer where the mother vernier of the overlay vernier will be formed; depositing a second polysilicon layer on the interlayer insulating film and the exposed first polysilicon layer; and patterning the second polysilicon layer to form the mother vernier.
|
申请公布号 |
US6391745(B1) |
申请公布日期 |
2002.05.21 |
申请号 |
US20000737807 |
申请日期 |
2000.12.18 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
KWON WON TAIK |
分类号 |
G03F1/08;G03F1/38;G03F1/42;H01L21/027;H01L21/301;H01L21/66;H01L23/544;(IPC1-7):H01L21/301 |
主分类号 |
G03F1/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|