| 摘要 |
The present invention relates to a semiconductor package and a fabricating method thereof, more particularly, to a chip size package of a wafer level and a fabricating method thereof. Accordingly, the present invention eases sufficiently the thermal stress generated from the difference of heat expansion rates between the semiconductor chip and the PCB substrate, increases the reliance of the wires as the stress on the wires are greatly reduced, simplifies the fabrication process, and reduces the product cost owing to simplified processes as equipments for metal deposition, metal plating and etch arc not necessary. The present invention, as embodied and broadly described, the present invention includes a semiconductor chip, a chip pad in a first area of the semiconductor chip, a stress-easing layer formed in a second area of the semiconductor chip, a conductive wire connecting the chip pad to the stress-easing layer, and an electrical conductor on the conductive wire over the stress-easing layer. And, the present invention includes the steps of forming a chip pad on a first area of a semiconductor chip, forming a stress-easing layer on a second area of the semiconductor chip, forming a conductive wire connecting the chip pad to the stress-easing layer, and forming a electrical conductor on the conductive wire over the stress-easing layer. |
