发明名称 Redundancy circuit of semiconductor memory
摘要 A semiconductor has eight banks that can be accessed simultaneously. Within each bank, there are disposed two fixed spare row decoders and two mapping spare row decoders. Within each bank, two fixed fuse sets are provided corresponding to the fixed spare row decoders. Eight mapping fuse sets are provided at the outside of each bank, for example, with no association with the mapping spare row decoders. Each mapping fuse set stores mapping data for determining a correspondence of the mapping fuse set to a specific mapping spare row decoder within a specific bank.
申请公布号 US6392937(B2) 申请公布日期 2002.05.21
申请号 US20010861843 申请日期 2001.05.22
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 NAGAI TAKESHI
分类号 H01L21/822;G11C5/00;G11C7/00;G11C11/34;G11C29/00;G11C29/04;H01L21/82;H01L27/04;(IPC1-7):G11C7/00 主分类号 H01L21/822
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