Method of selectively controlling contact resistance by controlling impurity concentration and silicide thickness

摘要

Methods are provided that selectively provide various contact resistances based on each individual transistor's influence on an overall chip speed during the formation of active regions and silicide layers. In order to provide lower contact resistance to devices which have a critical influence on overall device speed, the active regions of such critical devices are formed with a lower impurity concentration and thicker silicide layers are provided on the active regions. Likewise, for the normal devices which have less or no influence on overall chip speed, thinner silicide layers are provided on the active regions having a higher impurity concentration than the critical devices.