发明名称 Breaking replay dependency loops in a processor using a rescheduled replay queue
摘要 Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
申请公布号 AU3666802(A) 申请公布日期 2002.05.21
申请号 AU20020036668 申请日期 2001.10.18
申请人 INTEL CORPORATION 发明人 DOUGLAS M. CARMEAN;DARRELL D. BOGGS;DAVID J. SAGER;FRANCIS X. MCKEEN;PER HAMMARLUND;RONAK SINGHAL
分类号 G06F9/38 主分类号 G06F9/38
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