| 发明名称 |
Buried strap for DRAM using junction isolation technique |
| 摘要 |
A logic circuit including an embedded DRAM achieves process integration by simultaneously forming the strap connecting the memory cell capacitor with the pass transistor and a buried dielectric layer isolating the logic transistor sources and drains from the substrate.
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| 申请公布号 |
US6391703(B1) |
申请公布日期 |
2002.05.21 |
| 申请号 |
US20010894336 |
申请日期 |
2001.06.28 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ROVEDO NIVO;LAM CHUNG H.;MIH REBECCA D. |
| 分类号 |
H01L21/28;H01L21/8234;H01L21/8242;H01L27/06;H01L27/088;H01L27/108;H01L29/423;H01L29/49;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/28 |
| 代理机构 |
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代理人 |
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