发明名称 A system and method for sending and receiving data signals over a clock signal line
摘要 The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a returm channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.
申请公布号 AU2869902(A) 申请公布日期 2002.05.21
申请号 AU20020028699 申请日期 2001.10.30
申请人 SILICON IMAGE, INC. 发明人 GYUDONG KIM;MIN-KYU KIM;SEUNG HO HWANG
分类号 G06F13/38;G06F1/12;H04L1/12;H04L7/00;H04L7/04;H04L25/02;H04L25/38 主分类号 G06F13/38
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