| 摘要 |
<p>PURPOSE:To select a fetch timing as the result of discrimination and to decrease number of terminals. CONSTITUTION:A connection terminal is provided to a connection section of a timing setting circuit 41 triggered by a leading edge of a clock pulse to output a timing setting pulse with a time constant circuit 43. An input terminal of a selection signal generating circuit 44 is connected to a connection terminal T. When the time constant circuit 43 is connected to the connection terminal T via a selection switch SW, an output of an RS flip-flop FF5 of the selection signal generating circuit 44 goes to an H level by an increase in a terminal voltage of a capacitor C1. When the connection terminal T connects to ground via the selector switch SW, the output of the RS flip-flop FF5 of the selection signal generating circuit 44 goes to an L level. A selector 42 outputs a timing signal with a prescribed time width from a trailing edge of either the clock pulse or the timing setting pulse corresponding to the level at the output of the selection signal generating circuit 44.</p> |
