| 摘要 |
The page-erasable flash memory (MEM1) comprises a flash memory array (FMA), which contains transistors with floating gates connected to the word lines forming pages belonging to sectors (S1,S2...S8), and the control circuits comprising a counter (CMPT) formed by at least one row of transistors, the page address reading circuits including a shift register (SREG), a conversion circuit (CONVC), and a zero-detector (DETZ), and the counter increment circuits including the shift register and a programming register containing latches (LT). The circuits are connected so that the reprogramming of programmed transistors is carried out when the threshold voltage of transistors is below a set verification voltage. The page address reading circuits also comprise the counter word reading circuits including a counter decoder (CDEC), a sense amplifier (SA), the zero-detector, and a column address counter (CAC), the page address high-value bit delivery circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit delivery circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit delivery circuits including the column address counter and a multiplexer (MUX2). The circuits for the counter increment are connected for the programming of at least one counter transistor without erasing other transistors, and the transistor programmed at each increment is the next according to the direction of reading the counter. The page control circuits also comprise a row decoder (XDEC1) and the sense amplifier for reading a word of page by applying the first read voltage (Vread), for reading the same word of page by applying the second read, that is verify, voltage (Vvrfy), for comparing the two readings by a comparator (COMP), and for the reprogramming of transistors if the two readings (W1,W2) are different. The page erasing is by applying a positive erase voltage (Ver+) to the source or the drain electrodes of all transistors of the sector comprising the page. The row decoder (XDEC1) contains adapters for applying a polarization or a negative erase voltage (Vpol,Ver-) to the gates of transistors of the page to be erased, and for applying a positive inhibition or row decoder voltage (Vinhib,Vpcx) to the gates of transistors of one or more pages not to be erased. The adapter circuits receive a page selection signal and deliver the positive voltage (Vpcx) when teh page is not selected and the memory is in the erase mode, or when the page is selected and the memory is not in the erase mode, and the polarization voltage (Vpol), which is below the positive voltage (Vpcx), when the page is selected and the memory is in the erase mode, or when the page is not selected and the memory is not in the erase mode. During the page erasing the polarization voltage (Vpol) is equal to the erase voltage (Ver-) and the positive voltaage (Vpcx) is equal to the inhibition voltage (Vinhib); during the word reading the polarization voltage is equal to the ground potential and the positive voltage is equal to the read voltage. Each adapter circuit contains an output inverter stage and a control stage with an exclusive-OR gate. The positive erase voltage (Ver+) is applied to the source or the drain electrodes of transistors by the intermediary of a material forming the channel of transistors.
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