发明名称 |
SIDE WALL PROCESS FOR IMPROVING FLASH MEMORY CELL PERFORMANCE |
摘要 |
PROBLEM TO BE SOLVED: To provide a method of protecting the sides of laminated word lines during SAS etching to avoid the problem that the sides of the laminated word lines of flash memory cells are exposed during SAS etching and prevents an inter-polysilicon dielectric and a gate dielectric from being undercut to increase the data hold loss. SOLUTION: The method of manufacturing a flash memory having conductor lines (24) crossing a trench isolation structure (70) comprises forming nitride side walls (125) for protecting a laminate during an SAS etching process.
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申请公布号 |
JP2002141425(A) |
申请公布日期 |
2002.05.17 |
申请号 |
JP20010284530 |
申请日期 |
2001.09.19 |
申请人 |
TEXAS INSTR INC <TI> |
发明人 |
AMBROSE THOMAS M;MEHRAD FREIDOON;YUAN JESSIE |
分类号 |
H01L21/28;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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