| 摘要 |
PROBLEM TO BE SOLVED: To provide a technology that can easily optimize the characteristic of a PLL circuit depending on a system environment to which the PLL circuit is applied. SOLUTION: The PLL circuit is provided with a phase comparator means (202) that compares a phase of a reference clock signal with a phase of a feedback clock signal, a phase correction means (203) that corrects the phase of the clock signal outputted from an oscillation means depending on the result of phase comparison, a feedback loop (22) that feeds back the clock signal outputted from the oscillation means to the phase comparison means, and a phase correction amount adjustment means (207, 208) that adjusts the phase correction amount by the phase correction means in response to a ratio of a delay in the feedback loop to a phase comparison interval. The characteristic of the PLL circuit can be optimized through the adjustment of the phase correction amount in response to the ratio of the delay in the feedback loop to the phase comparison interval. |
