| 摘要 |
PROBLEM TO BE SOLVED: To provide a technique for reducing continuity resistance in a field- effect transistor. SOLUTION: This field-effect transistor 1 has a groove formed in a high- resistance layer 12, and upper- and lower-side cells 51 and 52 arranged on the surface of the high-resistance layer 12 and the bottom surface of the groove, respectively. The periphery of the upper-side cell 51 is surrounded by the groove, and the channel region is formed on the side of the groove. As a result, the entire periphery of the upper-side cell 51 becomes a channel region, and there is no need for securing area required for the channel region on the surface of the upper-side base region 29 in the upper-side cell 51, thus arranging a larger number of cells as compared with the lower-side cell 52 and the conventional cell, increasing the gate width per unit area in the upper-side cell 51 as compared with the conventional case, and hence reducing the continuity resistance.
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