DATA TRANSFER CONTROLLER AND ELECTRONIC DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a data transfer controller that can dynamically select a frequency of a generated clock signal without causing an improper operation and to provide an electronic device. SOLUTION: The data transfer controller includes a clock generating circuit 440 that generates clock signals CLKH, CLKF and a clock control circuit 450 that controls the clock generating circuit 440 and generates a system clock SYCLK on the basis of the clock signals CLKH, CLKF. The clock control circuit 450 enables the self-running operation of a PLL 60M generating the clock signal CLKF before disabling the self-running operation of a PLL 480M generating the clock CLKH and selects the generating clock of the SYCLK from the clock signal CLKH into the clock signal CLKF after the self-running operation of the PLL 60M is stabilized. The clock control circuit 450 sets the clock signal SYCLK to a '0' level only for a prescribed period on the condition that the clock signal CLKH reaches a '0' level and generates the clock signal SYCLK on the basis of the clock signal CLKF on the condition that the clock signal CLKF goes to a '0' level. In the changeover from an HS(High Speed) mode to an FS(Full Speed) mode in the USB 2.0, the clock control circuit 450 disables the operation of the PLL 480M to reduce the power consumption.