| 摘要 |
A memory accessing and controlling unit that controls the transfer of data between a CPU and a memory cluster. The memory accessing and controlling unit comprises a CPU interface circuit and a memory controlling circuit. When the CPU interface circuit picks up a data read request signal from the CPU, a corresponding internal data read request is forwarded to the memory controlling circuit. Next, the memory controlling circuit is sent out some controlling instructions to the memory cluster for reading out the requested data to the CPU. If the CPU also sends out an L1 write-back signal some time later, the memory controlling circuit immediately terminates the current reading operation so that data from the CPU can be written back to the memory cluster.
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