发明名称 |
Method and apparatus for performing multiply-add operations on packed data |
摘要 |
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. |
申请公布号 |
US2002059355(A1) |
申请公布日期 |
2002.05.16 |
申请号 |
US20010989736 |
申请日期 |
2001.11.19 |
申请人 |
INTEL CORPORATION |
发明人 |
PELEG ALEXANDER D.;MITTAL MILLIND;MENNEMEIER LARRY M.;EITAN BENNY;DULONG CAROLE;KOWASHI EIICHI;WITT WOLF |
分类号 |
G06F7/48;G06F7/52;G06F7/533;G06F7/544;G06F9/302;G06F15/78;G06F17/14;G06F17/16;G06T1/20;(IPC1-7):G06F7/00 |
主分类号 |
G06F7/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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