发明名称 Planarizing insulating region used in production of ULSI switches comprises forming connecting surface oxide layer, first nitride layer, and oxide sacrificial layer
摘要 Planarizing an insulating region comprises forming a connecting surface oxide layer (14), a first nitride layer (18), an oxide sacrificial layer and a second nitride layer on a substrate (10); forming a trench through the layers and in the substrate; depositing an oxide layer which fills the trench and extends over the second nitride layer; chemical-mechanical polishing the oxide layer and the second nitride layer so that the second nitride layer has a thickness of 50-200 Angstrom ; removing the second nitride layer and the oxide sacrificial layer; and chemical-mechanical polishing the oxide layer and the first nitride layer so that the upper surface of the oxide layer aligns within 10% of the upper surface of the first nitride layer. Preferred Features: The connecting surface oxide layer is 40-80 Angstrom thick. The first nitride layer is 600-1000 Angstrom thick. The oxide sacrificial layer is 100-200 Angstrom thick. The second nitride layer is 200-1500 Angstrom thick. The trench is 2500-3000 Angstrom deep in the substrate. The oxide layer is produced using HDPCVD.
申请公布号 DE10054190(A1) 申请公布日期 2002.05.16
申请号 DE20001054190 申请日期 2000.11.02
申请人 PROMOS TECHNOLOGIES, INC. 发明人 WU, CHAO-CHUEH
分类号 H01L21/3105;H01L21/762;(IPC1-7):H01L21/310;H01L21/302;H01L21/316;H01L21/76 主分类号 H01L21/3105
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