| 摘要 |
PURPOSE: A data write circuit of a semiconductor memory is provided, which reduces a data write time by writing data into a number of cells simultaneously during a parallel test of the semiconductor memory. CONSTITUTION: A memory cell array(260) stores data, and a Y-address predecoder(210) outputs addresses(AY0H<0:7>,AY3H<0:7>,AY6H<0:7>) by predecoding Y address(YADDR<0:8>) according to a clock(YCLK) by being enabled by a test mode signal(TEST). A Y-address decoder(220) determines eight line selection signals(YS<0>,YS<64>,YS<128>,...,YS<448>) among line selection signals(YS<0> -YS<511>) by processing addresses(AY0H<0:7>,AY3H<0:7>,AY6H<0:7>) from the Y-address predecoder. A sense amplifier part(250) is connected to a plurality of bit lines(BL,BLB) of the memory cell array, and amplifies external data to write to the memory cell array after the above eight line selection signals are determined. A main amplifier(230) outputs external input data to the sense amplifier part when an input/output selection signal(IOSW) is enabled. And an X-system control part(240) is enabled by a test mode signal(TEST) and outputs a word line signal(WL) to the memory cell array by calculating an X-address(XADDR) by a control command(CMD), and then drives a plurality of sense amplifiers by outputting control signals(CSP,CSN) to the sense amplifier part.
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