发明名称 |
Semiconductor memory device |
摘要 |
A semiconductor memory device including a memory cell array having a plurality of memory cells requiring refresh, a first internal address generation circuit, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and a second internal address generation circuit that operates in response to an output signal from the timer circuit. The first internal address generation circuit generates a refresh address of the entire memory region, and the second internal address generation circuit generates a refresh address of a certain part of the regions. By carrying out refresh of only a part of the memory required to be retained, the electric power consumption can be reduced.
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申请公布号 |
US2002057616(A1) |
申请公布日期 |
2002.05.16 |
申请号 |
US20010008709 |
申请日期 |
2001.11.13 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD |
发明人 |
OHTSUKA HIDEFUMI;YAMASAKI YUJI;FUJIMOTO TOMONORI |
分类号 |
G11C11/403;G11C11/406;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/403 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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