| 摘要 |
A fractional divider divides an input frequency of a first signal (Fi) by a rational, non-integral number, which rational number is greater than one and, when written as vulgar fraction, can only be written with a denominator not equal to one. The device comprises a number of series connected delay elements (a, b, c,..., R). Each of the delay elements (a, b, c,..., R) adds a predetermined delay to the signal of a previous delay element (a, b, ..., R-1). The first signal (Fi) is applied to the first delay element (a). The delay added again and again per delay element equals the period of the first signal (Fi) divided by the denominator of the vulgar fraction of the rational number. A counter (2) counts pulses of the first signal (Fi), which counting takes place modulo the numerator of the rational number and in steps of the denominator of the rational number. A decoder circuit (6) decodes counting scores of the counter (2), which appear successively at an output (6a, ..., 6e) of the decoder circuit (6) in dependence on the counting score and the algorithm. The combinatory circuit (6, 7, 8, 10, 11, 12, 13) comprises means (7, 8, 10, 11, 12, 13) for combining output signals of delay elements (a, b, ..., R) determined by the algorithm with output signals of the decoder circuit (6) so as to obtain the second signal (Fo). |
