| 摘要 |
PURPOSE: A data sensing device of a semiconductor memory is provided, which performs a reliable data sensing operation useful to a large integrated DRAM without using an additional signal for a precharge and an equalization in the DRAM, and reduces a mutual capacitance( or coupling capacitance) between bit line pairs in the DRAM. CONSTITUTION: A precharge/equalizer circuit(10) comprising serially connected NMOS transistors(M5,M6) is connected between bit line pairs(BLi,BLBi) of the ith block. And a precharge/equalizer circuit(20) comprising serially connected NMOS transistors(M7,M8) is connected between bit line pairs(BLj,BLBj) of the ith block. An isolation transistor(M1) is connected between the bit line(BLi) and a sensing node(SN), and an isolation transistor(M3) is connected between the sensing node and the jth bit line(BLj). An isolation transistor(M2) is connected between the bit line(BLBi) and a sensing node(SNB), and an isolation transistor(M4) is connected between the sensing node and the bit line(BJBj).
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