发明名称 APPARATUS FOR GENERATING ATM CELL ERRORS
摘要 PURPOSE: An apparatus for generating ATM cell errors is provided to enable an operator to check the existence of the abnormality of an encoder and a decoder. CONSTITUTION: An apparatus for generating ATM cell errors consists of the first memory(100), the second memory(200), the first MUX(300), the second MUX(400), and an error signal mixing part(500). The first memory(100), storing a plurality of single bit error values, transmits an 8-bit single bit error value to the first MUX(300) if an operator inputs a specific single bit error selection value using an input port(A1-A3). The second memory(200), storing a plurality of multiple bit error values, transmits an 8-bit multiple bit error value to the first MUX(300) if the operator inputs a specific multiple bit error selection value using an input port(B1-B3). The first MUX(300), if the 8-bit single bit error value and the 8-bit multiple bit error value are inputted from the first memory(100) and the second memory(200), passes either of the two error values to the second MUX(400) according to a cell selection signal(CS2) the operator selects. The second MUX(400), if the 8-bit single bit error value or the 8-bit multiple bit error value are inputted from the first memory(100) or the second memory(200), passes the inputted error value to the error signal mixing part(500) or interrupts it according to a cell selection signal(CS1) the operator selects. The error signal mixing part(500) mixes the 8-bit single bit error value or the 8-bit multiple bit error value with the 8-bit ATM cell data transmitted from an encoder(1), generates an ATM cell data error, and transmits it to a decoder(2).
申请公布号 KR20020035717(A) 申请公布日期 2002.05.15
申请号 KR20000066034 申请日期 2000.11.08
申请人 HYNIX SEMICONDUCTOR INC. 发明人 LIM, JAE GUK
分类号 H04L12/28;(IPC1-7):H04L12/28 主分类号 H04L12/28
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