| 摘要 |
<p>A bit slot synchroniser device including: a signal input port (52) for receiving a binary source signal; a clock input port (51) for receiving a clock signal, and a clock output port (54) for transmitting said clock signal; all ports being connected to synchroniser means (1) for synchronising said source signal and said dock signal, characterised in that said synchroniser means (1) include a number of cascaded partial synchronisation section (2,2',2") each section including: an input port (55) for receiving an input clock signal; a shifter device (3) connected to the input port for generating at least one shifted clock signal by shifting the phase of an input clock signal with a predetermined phase shift; a selection device (4) connected to the shifter device for selecting a selected clock signal from said input clock signal and said shifted clock signal based on a predetermined selecting criterion, and an output port (56) connected to the selection device for transmitting the selected dock signal further. <IMAGE></p> |
