发明名称 |
Non-blocking, multi-context pipelined processor |
摘要 |
<p>A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over. <IMAGE></p> |
申请公布号 |
EP1206084(A2) |
申请公布日期 |
2002.05.15 |
申请号 |
EP20010125448 |
申请日期 |
2001.11.05 |
申请人 |
ALCATEL INTERNETWORKING (PE), INC. |
发明人 |
VAN HOOF, WERNER;TALLEGAS, MATHIEU;WHEELER, JERROLD |
分类号 |
G06F15/78;H04L12/56;H04L29/06;(IPC1-7):H04L12/56;G06F9/38;G06F9/46 |
主分类号 |
G06F15/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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