发明名称 |
Method and apparatus for reducing the lock time of DLL |
摘要 |
A delay locked loop having improved synchronization times has a variably adjustable delay line which accepts two incoming clock pulses. As each pulse propagates through the delay line an edge of the pulse toggles or retoggles a shift bit corresponding to a delay element. When the first pulse reaches the end of the delay line, the status of the shift bits is frozen, and a starting point for a synchronization sequence begins at the transition point between toggled and retoggled shift bits.
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申请公布号 |
US6388480(B1) |
申请公布日期 |
2002.05.14 |
申请号 |
US20000649192 |
申请日期 |
2000.08.28 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
STUBBS ERIC T.;MILLER JAMES E. |
分类号 |
G06F1/10;H03L7/081;H03L7/10;(IPC1-7):H03L7/06 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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