发明名称 Method for reducing coefficient of thermal expansion in chip attach packages
摘要 A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably not B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.
申请公布号 US6387830(B1) 申请公布日期 2002.05.14
申请号 US19990265210 申请日期 1999.03.10
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BLUMBERG LAWRENCE ROBERT;JAPP ROBERT MAYNARD;RUDIK WILLIAM JOHN;SUROWKA JOHN FRANK
分类号 B32B5/28;H05K1/03;(IPC1-7):B32B5/26 主分类号 B32B5/28
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