Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same

摘要

A BIST circuit conducts an operation test on a memory cell array to detect a defective memory cell when power is turned on. On the basis of a result of the operation test, the BIST circuit generates a redundancy code indicative of a defect address corresponding to a defective memory cell. The redundancy code is transmitted to a repair determining circuit in a decoding circuit. The repair determining circuit stores the redundancy code in a volatile manner during the power is on. When an input address coincides with the redundancy code to be stored on the inside, the repair determining circuit executes an access to a corresponding spare memory cell area.