发明名称 |
Integrated circuit having forced substrate test mode with improved substrate isolation |
摘要 |
An integrated circuit is described which includes a test mode circuit that allows a substrate of the integrated circuit to be forced to a voltage level dictated by an external connection during a test operation, and provides an improved substrate isolation from the external connection during non-test operations. Both n-channel transistor and p-channel transistor isolation circuit embodiments are described. An integrated circuit memory device is described which incorporated the test mode and isolation circuits. The external connection can be coupled to a negative voltage during non-test operation which is more negative than a threshold voltage below a substrate voltage without inadvertently coupling the external connection and substrate together.
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申请公布号 |
US6388926(B1) |
申请公布日期 |
2002.05.14 |
申请号 |
US19990361009 |
申请日期 |
1999.07.27 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
GANS DEAN;DEVEREAUX KEVIN |
分类号 |
G01R31/317;G11C5/14;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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