发明名称 |
Semiconductor memory device outputting data according to a first internal clock signal and a second internal clock signal |
摘要 |
A semiconductor memory device outputs data in synchronization with an external clock signal. The semiconductor memory device comprises a first frequency divider dividing a frequency of the external clock signal supplied thereto so as to generate a first internal clock signal; a delay circuit delaying the external clock signal; a second frequency divider dividing a frequency of a signal supplied from the delay circuit so as to generate a second internal clock signal; and a data control unit outputting the data according to the first internal clock signal and the second internal clock signal.
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申请公布号 |
US6388945(B2) |
申请公布日期 |
2002.05.14 |
申请号 |
US20010811521 |
申请日期 |
2001.03.20 |
申请人 |
FUJITSU LIMITED |
发明人 |
AIKAWA TADAO |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C11/4076;G11C11/409;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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