| 摘要 |
A differential amplifier with adjustable offset includes a differential pair, a controller, an offset adjuster and an output stage. The differential pair and the output stage can be standard implementations such as, for example, a source-coupled PFETs and a folded-cascode output stage. The offset adjuster includes transistors that can be selectively enabled to form a composite transistor that is connected in parallel with at least one transistor of the differential pair to, in effect, increase the size of the transistor of the differential pair. The controller can reduce offset by causing the offset adjuster to increase the effective size of the appropriate transistor of the differential pair to compensate for device mismatch in the differential amplifier.
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