| 摘要 |
A computer readable storage medium has a logic synthesis code embodied therein. The logic synthesis code includes a standard design function for causing a computer to generate standard circuit information about target circuitry on which a logic synthesis function is to be performed, based on specifications of the target circuitry written in a hardware description language, the standard circuit information logically matching the specifications; a timing design function for causing the computer to generate modified circuit information by modifying the standard circuit information so that the standard circuit information satisfies both an ideal clock signal condition defining an ideal clock signal to be applied to one or more sequential circuits included in target circuitry, and at least either of a first ideal assertion period condition defining an ideal period of time during which each of one or more tristate buffers included in the target circuitry is asserted and a second ideal assertion period condition defining an ideal period of time during which each of one or more other sequential circuits for latching an output of a tristate buffer, which are included in the target circuitry is asserted; and an output function for outputting the modified circuit information from the timing design function.
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