发明名称 Integrated critical dimension control for semiconductor device manufacturing
摘要 A method and apparatus for reducing lot to lot CD variation in semiconductor wafer processing feeds back information gathered during inspection of a wafer, such as after photoresist application, exposure and development, to upcoming lots that will be going through the photolithography process, and feeds forward information to adjust the next process the inspected wafer will undergo (e.g., the etch process). Embodiments include forming a feature such as an etch mask on a semiconductor wafer at a "photo cell" by a photolithography process, then conventionally imaging the feature with a CD-SEM to measure its CD and other sensitive parameters. The measured parameters are linked, via the feature's SEM waveform, to photolithography adjustable parameters such as stepper focus and exposure settings. If the measured parameters deviate from design dimensions, the linked information on focus and exposure is fed back to the photo cell so the stepper can be adjusted, either automatically or at the user's discretion, to correct the deviation in following lots. The measured parameters are also linked to etch process adjustable parameters such as etch recipes for different over-etch and/or etch chemistry. If the measured parameters deviate from desired values, a linked etch recipe to correct the error is fed forward to the etcher and implemented automatically or at the user's discretion. This feedback and feed-forward mechanism improves lot to lot CD control at inspection following photoresist development and at final inspection as well.
申请公布号 US6388253(B1) 申请公布日期 2002.05.14
申请号 US20000703801 申请日期 2000.11.02
申请人 APPLIED MATERIALS, INC. 发明人 SU BO
分类号 H01L21/027;G03F7/20;H01L21/00;H01L21/02;H01L21/66;(IPC1-7):G01N23/225 主分类号 H01L21/027
代理机构 代理人
主权项
地址