Direct bit line-bit line defect detection test mode for SRAM

摘要

A system and method are disclosed herein for leakage testing of a static random access memory (SRAM) semiconductor memory device. Subtle leakage defects may be present in some devices in the early stages of SRAM production. These defects may later result in hard failures when packaged devices are burned in, but are not detected by functional tests performed during wafer sort. The leakage defects are associated with complementary bit line pairs within the SRAM matrix, and may be revealed by leakage current measurements made between all of the complementary bit line pairs within the SRAM. Comparatively minor modifications to the internal circuitry of the SRAM enable the leakage measurements to be performed during wafer sort, so defective devices can be screened out prior to packaging, lead-bonding, etc.