发明名称 |
Method and apparatus to synchronize a bus bridge to a master clock |
摘要 |
A method and apparatus for synchronizing a bus bridge to a master clock comprising receiving a time stamp packet at an input clock register of the bus bridge, comparing the value of the input clock register to the value of an output clock register of the bus bridge, obtaining an error value of the output clock register from the comparison, and determining whether the error value is below a predetermined threshold are described.
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申请公布号 |
US6389547(B1) |
申请公布日期 |
2002.05.14 |
申请号 |
US20000531063 |
申请日期 |
2000.03.18 |
申请人 |
SONY CORPORATION;SONY ELECTRONICS, INC. |
发明人 |
JAMES DAVID VERNON;FAIRMAN BRUCE;STONE GLEN DAVID |
分类号 |
G06F1/14;G06F13/40;H04J3/06;H04L12/18;H04L12/24;H04L12/28;H04L12/40;H04L12/46;H04L12/56;H04L12/64;H04L29/12;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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