| 摘要 |
PROBLEM TO BE SOLVED: To control an amplitude of an output signal of the clock phase variable circuit to be constant. SOLUTION: Sine waves Vsin(θ+π) and Vsin(θ) are given to input terminals in1, in2 respectively of a differential amplifier consisting of transistors (TRs) Q1, Q2 and Q3, Q4, from which differentially amplified signals are outputted from output terminals out1, out2. An amplitude detector 31 detects the amplitude of the output wave from the output terminal out1, a comparator 33 receives an output voltage of the amplitude detector 31 at its inverting input terminal and a reference voltage vref3 from a reference voltage generating circuit 32 is given to a noninverting input terminal of the comparator 33, and the comparator 33 provides an output of only a voltage proportional to the difference between the received signals to a base of a TR Q7. A current IEE of the TR Q7 is changed because the base voltage of the TR Q7 is changed. Thus, the amplitude of the output signal of the output terminal out1 is controlled to be constant thereby. A limiter amplifier circuit 11 receiving output signals from the output terminals out1, out2 whose amplitude is constant amplifies the signals differentially and provides an output. |
