发明名称 SEMICONDUCTOR DEVICE AND ITE MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To suppress a junction leakage and a contact leakage due to a misalignment while restraining the short channel effect, by reducing the dopant concentration of a substrate in a surface channel type PMOSFET. SOLUTION: In a CMOS of a dual-gate structure, a surface channel type PMOS whose gate electrode is formed with a P+ type poly-silicon film, is characterized in that arsenic or antimony is doped into the substrate under the gate electrode and nitrogen whose peak concentration is 2×1021/cm3 or more is doped into the gate oxide.
申请公布号 JP2002134629(A) 申请公布日期 2002.05.10
申请号 JP20000325604 申请日期 2000.10.25
申请人 SONY CORP;FUJITSU LTD 发明人 TSUKAMOTO MASANORI;IWABUCHI MAKOTO;HIZUYA KENICHI
分类号 H01L29/78;H01L21/8238;H01L21/8242;H01L27/092;H01L27/10;H01L27/108 主分类号 H01L29/78
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